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CADENCE PRODUCTS

System Design and Verification
	C-to-Silicon Compiler (252KB)
	Incisive検証IP (395KB)
	Incisive Enterprise Simulator (264KB)
Logic Design
	Encounter RTL Compiler (490KB)
	Cadence InCyte Chip Estimator (276KB)
Custom IC Design / RF Design
	Virtuoso platform L (770KB) Virtuoso platform XL (1.1MB) Virtuoso platform GXL (165KB) Silicon Analysis (272KB) Virtuoso Layout Migrate (102KB) Virtuoso Multi-mode Simulation (799KB)
Digital Implementation
	Encounter Digital Implementation System (354KB) Encounter Timing System (701KB)
Manufacturability Signoff (DFM)
	MaskCompose (316KB) Virtuoso RET Suite (562KB) PVS (251KB)
PCB Design / IC Package and SiP Design
	Design Creation Technology (338KB) Allegro FPGA System Planner (336KB) Allegro PCB Design (471KB) Allegro PCB RF Option (296KB) Allegro PCB SI (441KB) Allegro Design Workbench (375KB) CADENCE 3D Design Viewer (317KB) IC/Package Co-design (319KB) Allegro Package SI L (242KB) SiP Digital Design (209KB) SiP RF Design (270KB) Allegro PCB Librarian XL (311KB)