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・データシートはこちらより >> 　　・ホワイトペーパーはこちらより >>

データシート

System Design and Verification
	C-to-Silicon Compiler (396KB)
	Incisive Enterprise Manager (812KB)
	Incisive Enterprise Simulator (264KB)
	Incisive Formal Verifier (812KB)
	Palladium XP (243KB)

Functional Verification
	Cadence VIP Catalog (266KB) Cadence Verification IP for Memories (288KB)

Logic Design
	Cadence InCyte Chip Estimator (432KB)
	Encounter RTL Compiler (490KB)
	Encounter Conformal Constraint Designer (585KB)
	Encounter Conformal ECO Designer (257KB)
	Encounter Conformal Equivalence Checker (333KB)
	Encounter Conformal Low Power (291KB)

Custom IC Design / RF Design
	Virtuoso platform L (360KB) Virtuoso platform XL (1.1MB) Virtuoso platform GXL (165KB) Silicon Analysis (272KB) Virtuoso Layout Migrate (102KB) Virtuoso Multi-mode Simulation (799KB)　 Virtuoso Foundation IP Characterization (528KB)

Digital Implementation
	Encounter Digital Implementation System (386KB) Encounter Power System (607KB) Encounter Timing System (752KB) Virtuoso Digital Implementation (1.1MB)

Manufacturability Signoff (DFM)
	MaskCompose (316KB) Virtuoso RET Suite (562KB) PVS (260KB)

PCB Design
	Allegro Design Entry HDL,Allegro System Architecht, Allegro Design Publisher (347KB) Allegro FPGA System Planner (323KB) Allegro PCB Design: Layout and Routing (547KB) Allegro PCB RF Option (349KB) Allegro PCB Signal and Power Integrity (489KB) Allegro Librarian XL (341KB) Allegro Design Workbench (427KB) Cadece Schematic Capture (357KB) Cadence Activeparts Portal (223KB) Cadence OrCAD FPGA System Planner (362KB) Cadence OrCAD PCB Design Suites (597KB) Cadence OrCAD PCB Designer Place and Route (490KB) Cadence Simulation for PCB Design (509KB) Cadence OrCAD Signal Explorer Signal Integrity Technology (506KB)

IC Package and SiP Design
	Cadence IC/Package Co-Design (326KB) Cadence 3D Design Viewer (394KB) Cadence SiP Digital Design (240KB) Cadence SiP RF Design (286KB)

ホワイトペーパー

機能シミュレータ・パフォーマンスの改善 (458KB)
キャッシュコヒーレントインターコネクトの複雑性と検証およびパフォーマンス解析 (765KB)

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