製品情報&ソリューション

• Systems
• Enterprise Verification
• Low Power
• Mixed Signal
• Advanced Node(DFM)

• ChipEstimate.com
• PowerForward
• Cadence Connections Program
• OVM
• Cadence Verificatino Alliance

Services

• Functional Verification
• 検証IP
  • Incisive Verification IP
• テストベンチ・シミュレーション
  • Incisive Enterprise Specman Elite Testbench
  • Incisive Enterprise Simulator
  • Incisive Verification IP
  • UVM
  • OVM
• フォーマル解析
  • Incisive Enterprise Verifier
  • Incisive Formal Verifier
• 検証プロセス自動化
  • Incisive Enterprise Manager
  • Incisive Verification IP

• IC Packaging and SiP Design
• シグナル／パワー・インテグリティ
  • Allegro Package SI
  • Cadence SiP Digital SI
• ICパッケージ／SiP設計
  • Cadence SiP Digital Architect
  • Cadence SiP Digital Layout
  • Cadence SiP RF Architect
  • Cadence SiP RF Layout
  • Allegro Package Designer
  • Allegro PCB Librarian XL
  • Cadence 3D Design Viewer

• Manufacturability Signoff (DFM)
• マスクレイアウト
  • Cadence MaskCompose Reticle and Wafer Synthesis Suite
  • Cadence QuickView Layout and Manufacturing Data Viewer
• CMPサインオフ
  • Cadence CMP Predictor
• リソ・サインオフ
  • Cadence Litho Physical Analyzer
  • Cadence Litho Electrical Analyzer
• レイアウト検証
  • Cadence Physical Verification System
  • Assura Physical Verification

• PCB Design
• ライブラリ／データマネージメント
  • Allegro Design Workbench
  • Allegro PCB Librarian XL
• シグナル／パワー・インテグリティ
  • Allegro PCB SI
  • Cadence OrCAD Siglan Explorer
• FPGA
  • Allegro PCB Design
  • Cadence OrCAD PCB Designer
  • Cadence OrCAD PCB Designer Place and Route
• レイアウト／配線
  • Allegro FPGA System Planner
  • Cadence OrCAD FPGA System Planner
• フロント・エンド
  • Allegro Design Entry HDL
  • Allegro Design Entry CIS
  • Allegro Design Publisher
  • Allegro System Architect
  • Cadence OrCAD Capture/Caputure CID
  • Cadence Activeparts Portal

• Custom IC Design
• 寄生抽出／解析
  • Virtuoso Analog Design Environment
  • Cadence QRC Extraction
• レイアウト設計環境
  • Virtuoso Layout Suite
• シミュレーション環境
  • Virtuoso Analog Design Environment
  • Virtuoso Spectre Circuit Simulator
  • Virtuoso Accelerated Parallel Simulator
  • Virtuoso UltraSim Full-Chip Simulator
  • Virtuoso AMS Designer Simulator
• 回路設計環境
  • Virtuoso Schematic Editor
  • Virtuoso Multi-Mode Simulation

• Digital Implementation
• サインオフ解析
  • Encounter Digital Implementation
  • Encounter Timing System
  • Encounter Power System
  • Cadence QRC Extraction
  • Encounter Library Characterizer
• DFM最適化
  • Cadence Chip Optimizer
• 等価性検証
  • Encounter Conformal Equivalence Checker
  • Encounter Conformal Constraint Designer
  • Encounter Conformal ECO Designer
  • Encounter Conformal Low Power
• 配置・配線
  • Encounter Digital Implementation System
  • First Encounter Silicon Virtual Prototyping
  • NanoRoute Router
• Logic Design
• テスト
  • Encounter Test Architect
  • Encounter True-Time Test
• 論理合成
  • Encounter RTL Compiler
• チップ見積り
  • Cadence InCyte Chip Estimator
  • Cadence Chip Planning System

• System Design and Verification
• 高位合成
  • C-to-Silicon Compiler
• アクセラレーション/エミュレーション
  • Cadence Palladium XP
  • Incisive Palladium series
  • Incisive Palladium Dynamic Power Analysis
  • Cadence SpeedBridge Adapters
  • Incisive Xtreme series

Products A to Z